1. Field of the Disclosure
The present disclosure relates to a display device, and particularly, to a shift register for flat panel display devices and a method of driving the same.
2. Discussion of the Related Art
With the advance of various portable electronic devices such as mobile terminals and notebook computers, the demand for flat panel display devices applied to the portable electronic devices is increasing. Therefore, flat panel display devices such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and organic light emitting diode (OLED) display devices are being commercialized.
A gate driving circuit of the flat panel display devices includes a shift register for sequentially supplying a gate pulse to a plurality of gate lines. The shift register includes a plurality of stages including a plurality of transistors, and the stages are connected in cascade to sequentially output the gate pulse.
Recently, LCD devices and/or organic light emitting display devices use a gate-in panel (GIP) type in which the transistors configuring the shift register of the gate driving circuit are built into a substrate of a display panel as thin film transistors (TFTs).
The TFTs configuring the GIP type shift register supply the gate pulse to a plurality of pixels formed in the display panel, respectively. Therefore, in addition to fundamental characteristics of the TFTs such as a mobility and a leakage current, an electrical reliability and a durability for maintaining a service life for a long time are very important.
A semiconductor layer of the TFTs is formed of amorphous silicon or polycrystalline silicon. Amorphous silicon is simple in film-forming process and is low in manufacturing cost, but cannot secure an electrical reliability.
Moreover, polycrystalline silicon is very difficult to realize a large area due to a high process temperature, and cannot secure a uniformity based on a crystallization scheme. To solve such problems, research for using an oxide semiconductor as the semiconductor layer of the TFTs is being done recently.
An oxide semiconductor is amorphous, and is evaluated as a stable material. When using the oxide semiconductor as the semiconductor layer of the TFTs, the TFTs can be manufactured at a low temperature by using the existing process equipment even without additionally buying separate process equipment, and there are several advantages such as an ion injecting process being omitted, etc.
FIG. 1 is a graph showing a transfer characteristic of a general oxide TFT.
As seen in FIG. 1, since an oxide thin film transistor (hereinafter referred to as an oxide TFT) has a negative threshold voltage, a leakage current occurs when a gate voltage (Vg) is 0 V. Due to the leakage current, the shift register cannot output a normal gate pulse.
Such a problem can be solved by changing a manufacturing process of the oxide TFT to shift a threshold voltage of the oxide TFT to a positive voltage. However, since the TFTs formed in a display area of the display panel also have a positive threshold voltage (Vth), driving power increases. Therefore, a method is needed for lessening an influence of the threshold voltage corresponding to a weak point of the oxide TFT configuring the shift register.
The shift register includes a pull-up TFT for outputting a high voltage and a pull-down TFT for outputting a low voltage. Here, the pull-up TFT for outputting the high voltage is connected to a Q node, and the pull-down TFT for outputting the low voltage is connected to a QB node.
Here, the QB node holds the high voltage for most of time during one frame period. Accordingly, a threshold voltage of the pull-down TFT connected to the QB node is shifted to a positive voltage, and for this reason, a falling time operation is affected.
In the GIPT type shift register of the related art, when a layout for driving in one horizontal period (1HT) is set, it is difficult to change a timing of an output signal.
Especially, when a layout is set as a 1HT driving scheme, a signal cannot be outputted for a time equal to or longer than one horizontal period (1HT), and when a layout is set as a 2HT driving scheme, an output of a signal is inevitably adjusted in only a 2HT time corresponding to two horizontal period (2HT).
Since the related art shift register generates an output signal (VGH, VGL) by booting a clock signal (CLK), the output signal is affected by a width of the clock signal (CLK). It is required to increase the width of the clock signal for increasing an output time of a signal, but when the width of the clock signal increases, the shift register cannot normally operate because a high output signal (VGH) and a low output signal (VGL) overlaps.
In addition, multi signals, namely, various output signals, are needed for driving pixels of the OLED display device. However, the related art shift register cannot generate various output signals, and cannot adjust a timing of the output signals.